PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs

High-Performance Low-Power Cache Memory Architectures

Recent remarkable advances of VLSI technology have been increasing processor speed and DRAM capacity. However, the advances also have introduced a large, growing performance gap between processor and main memory. Cache memories have long been employed on processor chips in order to bridge the processor-memory performance gap. Therefore, researchers have made great efforts to improve the cache p...

Low-Power High-Performance Ternary Content Addressable Memory Circuits

Trends in High-Performance, Low-Power Cache Memory Ar- chitectures

One of uncompromising requirements from portable computing is energy efficiency, because that affects directly the battery life. On the other hand, portable computing will target more demanding applications, for example moving pictures, so that higher performance is still required. Cache memories have been employed as one of the most important components of computer systems. In this paper, we b...

Classification of Compiler Optimizations for High Performance, Small Area and Low Power in FPGAs

We propose a classification of high and low-level compiler optimizations to reduce the clock period, power consumption and area requirements in Field-programmable Gate Array (FPGA) architectures. The potential of each optimization, its effect on clock period, power and area and machine dependency is explained in detail.

A Low-Cost, High Performance Data Acquisition & Control Card Using LatticeECP/EC FPGAs and Lattice ispPAC Power Manager White Paper